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TDA9207
150MPIX VIDEO CONTROLLER WITH I C BUS FOR CRT & LCD MONITORS
2
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PRODUCT PREVIEW
150MHz PIXEL RATE 2.9ns RISE AND FALL TIME @ 120MHz/2VPP/5pF LOAD I2C BUS CONTROL GREY SCALE TRACKING VERSUS BRIGHTNESS OSD MIXING NEGATIVE FEED-BACK FOR DC-COUPLED CATHODES INTERNAL POSITIVE FEED-BACK FOR LCD APPLICATION 0.5 ~ 4.5V DACS FOR BLACK LEVEL RESTORATION (AC-COUPLED CATHODES) OR CUT-OFF CONTROLS WITH TDA9533 (ST VIDEO OUTPUT BUFFER FOR DC COUPLED CATHODES) BEAM CURRENT LIMITING PEDESTRAL CLAMPING ON OUTPUT STAGE SYNC CLIPPING POSSIBILITY OF LIGHT OR DARK GREY OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH BUILT IN CLAMPING PULSE STAND-BY MODE 5V TO 8V POWER SUPPLY
SHRINK DIP24 (Shrink Plastic Package) ORDER CODE : TDA9207
DESCRIPTION The TDA9207 is a monolithic integrated RGB preamplifier for color Monitors with I2C Bus Control and On-Screen Display. The classical Contrast, Brightness, Drive and CutOff Controls are provided. On Top of that, additional functions have been integrated as follows : - OSD contrast, - Bandwidth adjustment, - Grey background, - Internal back porch clamping pulse generator.
August 1998
The RGB incoming signals are amplified and shaped, to drive all commonly used Video buffer without intermediate follower stage. Eventhrough encapsulated in 24 pins package only, the IC allows any kind of CRT Cathode coupling : - AC coupled with DC restore, - DC coupled with Feed-Back from Cathodes, - DC coupling with Cut-Off controls on Video Output buffer (with TDA9533). The IC, as any ST Video preamplifier, is designed in such a way to be able to drive real load without external interface. A very typical advantage of ST devices is their ability to sink and source currents, while most of competitive devices have problem to sink large current. Thanks to the original internal output stage structure, those driving capabilities are combined with low Power Dissipation as there is not static current consumption in the output pins. All together, the large integration combined with high performance and advanced features make the TDA9207 one of the best choice for any CRT Monitor ranging from 14" to 17". Combined with TDA910x (H/V processor) ; TDA9533 (Video amplifier) ; STV942x (OSD) and ST72xx (MCU), the TDA9207 allows to realize high performance and cost optimized application.
1/17
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA9207
PIN CONNECTIONS
IN1 ABL IN2 GNDL IN3 GNDA VCCA VDDL OSD1 OSD2 OSD3 FBLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BLK HSYNC or BPCP CO1/FB1 OUT1 VCCP OUT2 GNDP OUT3 CO3/FB3 CO2/FB2 SDA SCL
9207-01.EPS 9207-01.TBL
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol IN1 ABL IN2 GNDL IN3 GNDA VCCA VDDL OSD1 OSD2 OSD3 FBLK SCL SDA CO2/FB2 CO3/FB3 OUT3 GNDP OUT2 VCCP OUT1 CO1/FB1 HSYNC BPCP BLK Function Red Video Input ABL Input Green Video Input Logic Ground Blue Video Input Analog Ground Analog VCC Logic VDD Red OSD Input Green OSD Input Blue OSD Input Fast Blanking SCL SDA Green Cut-off Output/Feedback Input Blue Cut-off Output/Feedback Input Blue Video Output Power Ground Green Video Output Power VCC Red Video Output Red Cut-off Output/Feedback Input HSYNC BPCP Blanking Input
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TDA9207
BLOCK DIAGRAM
BLK 24 FBLK 12 OUTPUT CLAMP PULSE (OCL) VCCP 20
TDA9207
CLAMP IN1 1
VREF OUTPUT STAGE
21 OUT1 22 CO1/FB1 18 GNDP
19 OUT2 IN2 3 GREEN CHANNEL 15 CO2/FB2
17 OUT3 IN3 5 BLUE CHANNEL 16 CO3/FB3 ABL 2 CONT/8bits BPCP LATCHES D/A GNDL GNDA VCCA VDDL 4 6 7 8 23 HSYNC or BPCP 14 13 9 OSD1 10 OSD2 11 OSD3
9207-02.EPS
BRT/8bits
Drive 3x8bits
Cut-off 3x8bits
I2C BUS DECODER OSD CONT (4 bits) I2C
Output DC Level Adjust (4 bits)
VREF SDA SCL
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TDA9207
FUNCTIONAL DESCRIPTION 1 - Input Stage The R, G and B signals must be fed to the 3 inputs through coupling capacitors (100nF). The maximum input peak-to-peak Video amplitude is 1V. The input stage includes a clamping function. This clamp uses the input serial capacitor as a "memory capacitor". In order to avoid a discharge of the serial capacitor during the line (due to leakage current), the input voltage is referenced to the ground. The clamp is gated by an internally generated "Back Porch Clamping Pulse" (BPCP). Register 8 allows choice of the way to generate BPCP (see Figure 1) : - When bit 0 is set to 0, BPCP is synchronized on the trailing or leading edge of HSYNC (Pin 23) (bit 1 = 0 : trailing edge, bit 1 = 1 : leading edge). Thanks to an automatic function, the IC is able to work with positive or negative HSYNC pulse.. - When bit 0 is set to 1, BPCP is synchronized on the leading edge of the blanking pulse BLK (Pin 24). One can use positive or negative blankFigure 1
R8b0 = 0 and R8b1 = 0 HSYNC/BPCP (Pin 23) Internal BPCP R8b0 = 0 and R8b1 = 1 HSYNC/BPCP (Pin 23) Internal BPCP R8b0 = 1 BLK (Pin 24) Internal BPCP R8b4 = 1 HSYNC/BPCP (Pin 23) Internal BPCP
9207-03.EPS
ing pulse by programming bit 0 in Register 9. - BPCP width can be adjusted with bit 2 and 3 (see Register 8 table). - In case of application provides already the Back Porch Clamping Pulse, bit 4 must be set to 1 (direct connection between Pin 23 and internal BPCP is provided). A sync clipping function is provided on channel 2. In the case of input signal voltage is lower than reference voltage (SOG standard for example), output voltage is set to the brigthness voltage (VBRT). As a matter of fact, no voltage below the brigthness voltage can be obtained on output signals and unbalance colors can't occur whatever the standard is. To validate this function, bit 7 in Register 9 must be set to 1. 2 - Contrast Adjustment (8 bits) The contrast adjustment is made by controlling simultaneously the gain of the 3 internal amplifiers through I2C bus interface. Register 1 allows adjustment in a range of 48dB.
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TDA9207
FUNCTIONAL DESCRIPTION (continued) 3 - ABL Control The TDA9207 includes an ABL input (automatic beam limitation) in order to attenuate R, G, B Video signals according to beam intensity. The operating range is to 2V typically (from 3V to 1V). A typical 15dB maximum attenuation is applied to the signal wathever the contrast adjustment is. Refer to Figure 2 for ABL attenuation range. In case of ABL feature is not used, ABL input (Pin 2) must be connected to 5V supply voltage. Figure 2
Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 VABL (V) 0 1 2 3 4 5
9207-04.EPS
-14 -16
4 - Brightness Adjustment (8 bits) Brightness adjustment is controlled by I2C bus thanks to Register 2. It consists to add the same DC voltage to the 3 R, G, B signals after contrast adjustment. This voltage is present only outside the blanking pulse (see Figure 3). It can be adjusted in the range of 0V to 2V with 8mV step. The DC output level during the blanking pulse is forced to "INFRA BLACK" level (VDC). 5 - Drive Adjustment (3 x 8 bits) In order to adjust the white balance, the TDA9207 offers the possibility to adjust separately the overall gain of each channel thanks to I2C bus (Registers 3, 4 and 5). The very large drive adjustment range (48dB) allows different standard or custom color temperature. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for end-user only. The drive adjustment is located after the Contrast, Brightness and OSD switch blocks, so that the white balance will remains correct when BRT is adjusted, and will also be correct on OSD portion of the signal.
6 - OSD Inputs The TDA9207 includes the circuitry to mix OSD signals into the RGB main picture. Four pins are dedicated to this function as follow : - 3 TTL RGB inputs (Pins 9, 10, 11) which are connected to the 3 outputs of the corresponding OSD processor, - one TTL fast blanking input (Pin 12) also connected to the FBLK output of the OSD processor. When a high level is present on FBLK, the IC will acts as follow : - The 3 main picture RGB input signals are internally switched to the internal input clamp reference voltage. - The 3 output signals are set to the voltage corresponding to the 3 OSD input logic states (0 or 1) (see Figure 3). If OSD input is low level, output equals brightness voltage (VBRT). If OSD input is high level, output equals VOSD where VOSD = VBRT + OSD and OSD is an I2C bus controlled voltage. OSD varies between 0V to 4.5V by step of 300mV thanks to Register 7 (4 bits). The same variation is applied simultaneously on the 3 channels providing an OSD contrast. Grey color can be obtained on output signals if : - OSD1 = 1 and OSD2 = 0 and OSD3 = 1 - and if a special bit (bit 5 or 6) in Register 9 is set to 1. If R9b5 is set to 1, light grey is obtained on output. If R9b6 is set to 1, dark grey is obtained on output. In the case of R9b5 and R9b6 are set to 0, normal operation is provided on output signals. 7 - Output Stage The 3 output stages are large bandwidth output amplifiers able to deliver up to 4.6VPP for 0.7VPP on input. When high level is applied on BLK input (Pin 24), the 3 outputs are forced to "INFRA BLACK" level (VDC) thanks to a sample and hold system (see here after). The black level (which is the output voltage outside the blanking pulse with minimum brightness and no Video input signals) is 400mV higher than VDC. The brightness level (VBRT) is then obtained by programming the corresponding register. The sample and hold system allows control of the "INFRA BLACK" level in the range of 0.5V to 2.5V thanks to Register 6 (in case of AC coupling) or Registers 10, 11, 12 (in case of DC coupling). Refer to "CRT cathode coupling" part for further details.
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TDA9207
FUNCTIONAL DESCRIPTION (continued) The overall waveforms of the output signal are shown in Figures 3 and 4. In the case of blanking pulse is not applied on TDA9207, an additional feature allows the connection of internal BPCP to the sample and hold system so that the output DC level is still I2C controlled. Figure 3 : Waveforms VOUT, BRT, CONT, OSD
HSYNC BPCP BLK Video IN FBLK OSD IN VOUT1, VOUT2, VOUT3 VCONT (4) VOSD (5) VBRT (3) VBLACK (2) VDC (1)
Notes : 1. 2. 3. 4. 5.
For that purpose, bit 7 in Register 8 must be set to 1. Then more, in order to simplify the application, it is possible to supply the power VCC with 5V (instead of 8V nominal) at the expense of output swing voltage.
OSD
CONT BRT 0.4V fixed
Figure 4 : Waveforms (DRIVE adjustment)
HSYNC BPCP BLK Video IN FBLK OSD IN VOUT1, VOUT2, VOUT3 VCONT VOSD VBRT VBLACK VDC Two exemples of drive adjustment (1)
Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT and VOSD. Drive adjustment do not modify the following voltages : VDC and VBLACK.
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9207-06.EPS
9207-05.EPS
VDC = 0.5 to 2.5V VBLACK = VDC + 0.4V VBRT = VBLACK + BRT (with BRT = 0 to 2V) VCONT = VBRT + CONT with CONT = k x Video IN (CONT = 4.6VPP max. for VIN = 0.7VPP) VOSD = VBRT + OSD (OSD max. = 4.5VPP, OSD min. = 0.3VPP)
TDA9207
FUNCTIONAL DESCRIPTION (continued) 8 - Bandwidth Adjustment A new feature, bandwidth adjustment, has been implemented on TDA9207. This function has several advantages : - Depending an external capacitive load and on pic to pic output voltage, bandwidth can be adjusted in order to avoid any slew-rate phenomenon (see Table 1 here after and refer to Register 13 description). - Since it is possible to slew down signal rise/fall time at the CRT driver input without affecting too much rise/fall time at the CRT driver output, preamp bandwidth can be adjusted in order to reduce electromagnetic radiation. - As the preamp bandwidth adjustment permits also to adjust the rise/fall time on the cathode (through the CRT driver), it is possible to optimize the frequency response / CRT driver power consumption ratio for any kind of chassis. - In picture mode, when high Video voltage swing is of great interest at the expense of rise/fall time, bandwidth adjustment may be the right way to avoid any slew rate phenomenon at the CRT driver output and to fit with electromagnetic radiation requirements. Table 1 : Recommendation for bandwidth adjustment
1.5pF TBD TBD TBD CLOAD 5pF 120MHz 100MHz TBD 10pF TBD TBD TBD
back input, the IC provides several kind of CRT cathode coupling. 9.1 - AC coupling with DC restore (see Figure 5) In this mode, output DC level (VDC) is adjusted simultaneously for the 3 channels from 0.5V to 2.5V thanks to Register 6 (4 bits). The cut-off voltage is programmed independently for each channel from 0.5V to 4.5V with the help of registers 10, 11, 12 (3 x 8 bits). 9.2 - DC Coupling with cut-off controls on Video Amplifier (with TDA9533) The functionning of the TDA9207 and the way to program it are the same as in the previous mode. But now, the cut-off control is made at the Video amplifier input (see Figure 6). In AC coupling and in DC coupling with cut-off control, bits 2, 3 and 4 in Register 9 must be set to 1. 9.3 - DC Coupling Mode In this mode, the cut-off level is controlled at the output of the preamp. So, output DC level (VDC) is adjusted independently for each channel from 0.5V to 2.5V via registers 10, 11 and 12 (see Figure 7). In DC coupling mode, bit 2 must be set to 1 and b3 to 0 in Register 9. 9.4 - DC Coupling with feedback mode The feedback voltage coming from the cathode is sent to the TDA9207. The sample and hold system compares this voltage with a reference coming from the cut-off DC level DAC and controls the DC voltage on the feedback input in the range of 0.5V to 2.5V. Each channel is controlled independently thanks to Registers 10, 11 and 12 (see Figure 8). In DC coupling with feedback mode, bit 2 and bit 4 must be set to 0 in Register 9.
Video Output Voltage 2VPP 3VPP 4VPP
9 - CRT Cathode Coupling Thanks to the multiplex of cut-off output and feedFigure 5
TDA9207
Pins 17-19-21
CRT Driver
CRT
DC LEVEL (4 bits) 0.5V to 2.5V
9207-07.EPS
CUT-OFF 1,2,3 DC LEVEL 0.5V to 4.5V (8 bits)
Pins 15-16-22
Cut-off Control
7/17
TDA9207
FUNCTIONAL DESCRIPTION (continued) Figure 6
TDA9207
CRT
Pins 17-19-21
TDA9533
DC LEVEL (4 bits) 0.5V to 2.5V
9207-08.EPS
CUT-OFF 1,2,3 DC LEVEL 0.5V to 4.5V (8 bits)
Pins 15-16-22
Figure 7
TDA9207
Pins 17-19-21
CRT Driver
CRT
Figure 8
TDA9207
Pins 17-19-21
CRT Driver
CRT
Pins 15-16-22 CUT-OFF 1,2,3 DC LEVEL 0.5V to 2.5V (8 bits)
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9207-10.EPS
9207-09.EPS
CUT-OFF 1,2,3 DC LEVEL 0.5V to 2.5V (8 bits)
TDA9207
FUNCTIONAL DESCRIPTION (continued) 10 - Stand-by Mode A stand-by mode is implemented on the IC. As soon as the power VCC (Pin 20) falls down below 3V typically, the device enters in stand-by mode wathever the voltage on analog VCC (Pin 7) and on logic VDD (Pin 8) is. In this case, all the analog part biases are internally switched-off while the logic parts (I2C bus, power-on reset) are still supplied. As a matter of fact, the corresponding power consumption is lower than 50mW in stand-by mode. 11 - Serial Interface The 2 wires serial interface is an I2C interface. The slave address of TDA9207 is DC hex.
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
MCU must send (see Figure 9). : - the I2C address slave byte with a low level for the R/W bit, - the byte to the internal register address where the MCU wants to write data, - the data. All bytes are sent MSB bit first and the write data transfer is closed by a stop. When transmitting several datas, it is possible to send before the stop as many as needed register address plus data without sending start and slave address. 12 - Power-on Reset A power-on reset function is implemented on the TDA9207 so that the I2C registers are in a well known status after power-on. Typical threshold for a rising supply on logic VDD (Pin 8) is 3.8V. It has some hysteresis and I2C registers are reseted as soon as VDD falls below 3.2V.
The host MCU can write into the TDA9207 registers. Read mode is not available. To write data into the TDA9207, after a start, the Figure 9 : I2C Write Operation
SCL SDA Start I2C Slave Address W ACK A7 A6 A5 A4 A3
A2
A1
A0 ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK Stop
Register Address
Data Byte
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9207-11.EPS
TDA9207
ABSOLUTE MAXIMUM RATINGS
Symbol VS VS VSPW VIN VINVIDEO Parameter Supply Voltage on Analog VCC Supply Voltage on Logic VDD Supply Voltage on Power VCC Voltage at any Input Pins (except Video inputs) and Input/Output Pins Voltage at Video Inputs 1, 3, 5 Pin 7 8 20 Value 5.5 5.5 8.8 5.5 1.4 Unit V V V V V
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Max. Value 69 Unit
o
C/W
DC ELECTRICAL CHARACTERISTICS Tamb = 25oC, VCCA = 5V, VDD = 5V, VCCP = 8V unless otherwise specified
Symbol VS VS VSPW ICC ICCP VI VOR VIL VIH IIN Supply Voltage Parameter Test Conditions Analog VCC (Pin 7) Logic VDD (Pin 8) Power VCC (Pin 20) Analog VCC and VDD Power VCC 0.5 OSD, FBLK, BLK, HSYNC 2.4 OSD, FBLK, BLK, HSYNC -1 1 Min. 4.5 4.5 4.5 Typ. 5 5 8 75 52 0.7 1 7 0.8 Max. 5.5 5.5 5.8 Unit V V V mA mA VPP VDC
9207-04.TBL
Supply Current Supply Current Video Input Voltage Amplitude Typical Output Voltage Range Low Level Input Voltage High Level Input Voltage Input Current
V V A
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9207-03.TBL
9207-02.TBL
TDA9207
AC ELECTRICAL CHARACTERISTICS Tamb = 25oC, VCCA = 5V, VDD = 5V, VCCP = 8V, VI = 0.7VPP, CLOAD = 5pF, unless otherwise specified
Symbol VI Parameter Video input Voltage Amplitude Test Conditions Contrast and Drive at maxi Min. Typ. 0.7 Max. 1 Unit VPP VIDEO INPUTS (Pins 1,3,5) VIDEO OUTPUTS (Pins 17,19,21) VIDEO SIGNAL GAM Maximum Gain VOM VON CAR DAR GM tR tF BW Maximum Video Output Voltage (peak-to-peak) Nominal Video Output Voltage (peak-to-peak) Contrast Attenuation Range Drive Attenuation Range Gain Matching Rise time Fall time Large Signal Bandwidth Bandwidth Adjustement Range CT Crosstalk between Video Outputs Contrast and Drive at maxi (CRT = DRV = 254dec) Contrast and Drive at maxi (CRT = DRV = 254dec) Contrast and Drive at POR (CRT = DRV = 180dec) Contrast maxi (CRT = 254dec) to Contrast mini (CRT = 1dec) Drive maxi (DRV = 254dec) to Drive mini (DRV = 1dec) Contrast and Drive at POR VOUT = 2VPP (BW = 15dec) VOUT = 3VPP (BW = 7dec) VOUT = 2VPP (BW = 15dec) VOUT = 3VPP (BW = 7dec) Minimum bandwidth (BW = 0dec) Maximum bandwidth (BW = 15dec) VOUT = 2.3VPP @ f = 10MHz @ f = 50MHz Brightness at maxi (BRT = 255dec) Drive at maxi (DRV = 254dec) Brightness at mini (BRT = 0dec) Drive at maxi (DRV = 254dec) Brightness and Drive at POR 16.4 4.6 2.3 48 48 0.1 2.9 3.6 120 100 80 120 70 35 2 0 0.4 20 dB VPP VPP dB dB dB ns ns MHz MHz MHz MHz dB dB VPP VPP V mV
VIDEO SIGNAL - BRIGTHNESS BRTmax Maximum Brightness Level BRTmin Minimum Brightness Level
VIP Insertion Pulse BRTM Brightness Matching VIDEO SIGNAL - OSD
Drive at maxi (DRV = 254dec) OSDmax Maximum OSD Output Level OSD at maxi (OSD = 15dec) OSDmin Minimum OSD Output Level OSD at mini (OSD = 0dec) VIDEO SIGNAL - DC LEVEL (AC COUPLING MODE) DCLmax Maximum Output DC Level DCL at maxi (DCL = 15 dec) DCLmin Minimum Output DC Level DCL at mini (DCL = 3 dec) VIDEO SIGNAL - DC LEVEL (DC COUPLING MODE) DCLmax Maximum Output DC Level Cut-off at maxi (Cut-off = 255dec) DCLmin Minimum Output DC Level Cut-off at mini (Cut-off = TBD) CUT-OFF OUTPUTS /FEEDBACK INPUTS (Pins 15,16,22) CUT-OFF OUTPUTS (AC COUPLING MODE) COmax Maximum Cut-off Output Voltage Cut-off at maxi (Cut-off = 255dec) (Sourced current = 200A) COmin Minimum Cut-off Output Voltage Cut-off at mini (Cut-off = 0dec) (Sinked Current = 2mA) COTD Cut-off Output Voltage Drift Tj Variation = 100C FEEDBACK INPUTS (DC WITH FEEDBACK MODE) Controlled Feedback Input Level VFBmax Maximum Cut-off at maxi (Cut-off = 255dec) VFBmin Minimum Cut-off at mini (Cut-off = TBD) IFB Input Current on Feedback Inputs V 2.5V
4.5 0 2.5 0.5 2.5 0.5
VPP VPP V V V V
4.5 0.5 TBD
V V mV
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9207-05.TBL
2.5 0.5 -1
V V A
TDA9207
AC ELECTRICAL CHARACTERISTICS (continued) Tamb = 25oC, VCCA = 5V, VDD = 5V, VCCP = 8V, VI = 0.7VPP, CLOAD = 5pF, unless otherwise specified
Symbol ABL (PIN 2) GABLmin ABL Mini Attenuation GABLmax ABL Maxi Attenuation VABL IABLhigh IABLlow ABL Threshold Voltage ABL Input Current VABL 3V VABL = 1V For output attenuation VABL = 3V VABL = 1V 0 15 3 0 -2 dB dB A A
9207-05.TBL 9207-12.EPS 9207-08.TBL 9207-07.TBL
Parameter
Test Conditions
Min.
Typ. Max. Unit
V
I2C ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Symbol VIL VIH IIN fSCL(Max.) VOL Parameter Low Level Input Voltage High Level Input Voltage Input Current (Pins SDA, SCL) SCL Maximum Clock Frequency Low Level Output Voltage SDA Pin when ACK Sink Current = 6mA 0.4V < VIN < 4.5V Test Conditions On Pins SDA, SCL 3 -10 200 0.6 +10 Min. Typ. Max. 1.5 Unit V V A kHz V
I2C INTERFACE TIMINGS REQUIREMENTS (see Figure 12)
Symbol tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL Parameter Time the bus must be free between 2 access Min. 1300 600 600 1300 600 300 250 20 300 Typ. Max. Unit ns ns ns ns ns ns ns ns
Figure 10
tBUF SDA tHDS SCL tHIGH
tHDAT tSUDAT tSUP tLOW
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TDA9207
I2C REGISTER DESCRIPTION Registers Sub-address
Sub-address Hex 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Dec 01 02 03 04 05 06 07 08 09 10 11 12 13 Contrast (CRT) Brightness (BRT) Drive 1 (DRV) Drive 2 (DRV) Drive 3 (DRV) Output DC Level (DCL) OSD Contrast (OSD) BPCP & OCL Miscellaneous Cut Off Out 1 DC Level (Cut-off) Cut Off Out 2 DC Level (Cut-off) Cut Off Out 3 DC Level (Cut-off) Bandwidth Adjustment (BW) Register Names 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC 4-bit DAC See Table See Table 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC POR Value Hex B4 B4 B4 B4 B4 09 09 04 1C B4 B4 B4 07 Dec 180 180 180 180 180 09 09 04 28 180 180 180 07 255 255 255 15 Max. Value 254 255 254 254 254 15 15
Note : For Contrast & Drive adjustement, code 01 (dec) and 255(dec) are not allowed. For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed. For Cut Off Output DC Level, output voltage is linear between code TBD and code TBD.
BPCP & OCL Register (R8)
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Function BPCP Source = HSYNC BPCP Source = BLK HSYNC edge = trailing HSYNC edge = leading BPCP Width = 0.33s BPCP Width = 0.66s BPCP Width = 1s BPCP Width = 1.33s BPCP Source = HSYNC BPCP Source = BPCP input Normal Operation Force BPCP to 1 (for test) Normal Operation Force OCL to 1 (for test) OCL Source = BLK input OCL Source = BPCP x x x x x x POR Value x
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TDA9207
I2C REGISTER DESCRIPTION (continued) Miscellaneous Register (R9)
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 1 x 0 0 0 0 1 0 1 0 1 0 0 1 0 x 1 1 0 Function Positive Blanking Polarity Negative Blanking Polarity Soft Blanking = OFF Soft Blanking = ON AC Coupling Mode DC Coupling Mode DC Coupling with Feedback Mode Light Grey on OSD Ouputs = OFF Light Grey on OSD Ouputs = ON Dark Grey on OSD Ouputs = OFF Dark Grey on OSD Ouputs = ON SOG Clipping = OFF SOG Clipping = ON x x x x x POR Value x
Bandwidth Adjustment (R13)
b7 b6 b5 b4 b3 1 0 0 0 0 1 0 1 0 b2 1 1 0 b1 1 1 0 b0 1 1 0 120MHz 100MHz 80MHz Normal Operation BW DAC output connected to BLK input (for test) BW DAC complementary output connected to BLK input (for test) x x Function POR Value
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TDA9207
INTERNAL SCHEMATICS Figure 11
VCCA
Figure 12
30kW
VCCA 1kW
IN (Pins 1-3-5)
HIGH IMPEDANCE
ABL
2
GNDA
9207-13.EPS 9207-14.EPS
GNDA
Figure 13
Figure 14
VCCA
VCCA
7 (8V)
GNDL
4
9207-15.EPS
GNDA
6
Figure 15
VCCA
Figure 16
VCCA OSD-FBLK-HS-BLK Pins 9-10-11-12 23-24 GNDA GNDL VDDL
VDDL
8
LOGIC PART
9207-17.EPS
GNDA
Figure 17
VCCL 30kW (8V) 4pF GNDA GNDL
Figure 18
VCCA
SDA-SCL Pins 13-14
CO/FB Pins 15-16-22
9207-19.EPS
GNDA
15/17
9207-20.EPS
9207-18.EPS
9207-16.EPS
GNDA
TDA9207
INTERNAL SCHEMATICS (continued) Figure 19
VCCP 20
VCCP
Figure 20
OUT Pins 17-19-21 (20V)
9207-21.EPS
GNDP 18
9207-22.EPS
GNDA
GNDA
GNDP
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TDA9207
PACKAGE MECHANICAL DATA 24 PINS - PLASTIC DIP (SHRINK)
E E1
A1
A2
Stand-off B B1 e e1 e2
L
A
c D E
24
13
F
.015 0,38 Gage Plan e
1
12 e3
SDIP24
e2
Dimensions A A1 A2 B B1 C D E E1 e e1 e2 e3
Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86
Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240
Inches Typ.
Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270
SDIP24.TBL
3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62
0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30
10.92 1.52
0.430 0.060
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